The present invention relates, in general, to the field of integrated circuit (“IC” or “chip”) devices. More particularly, the present invention relates to a circuit and a corresponding method of operation for limiting undesirable leakage current in a standby mode.
Powergating logic and decoding functions is a way to decrease the leakage current of turned-off transistors during standby for memory and other types of integrated circuits. By inserting a transistor in series with the power supply or ground or both and turning off this transistor during standby, power can be conserved. Powergating transistors, however, are large and can be leaky in prior art circuits. With today's high speed, low supply voltage products, leakage or off current and corresponding power consumption is becoming a significant factor. This problem is even more pronounced when a battery is used in, for example, wireless or portable applications.
Previous designs have taken the control gate of these powergating transistors to a level beyond the power supply voltage so that a negative VGS develops and the leakage is reduced further during standby.
Referring now to FIG. 1, three typical prior art powergated MOS circuits 10, 20, and 30 are shown. Circuit 10 includes a single P-channel transistor 12 in series with a typical MOS circuit 14, such as a memory IC or the peripheral logic circuit of a memory IC. The gate of P-channel transistor 12 is designated node “A”. Circuit 20 includes a single N-channel transistor 16 in series with MOS circuit 14. The gate of N-channel transistor 16 is designated node “B”. Circuit 30 includes both P-channel transistor 12 and N-channel transistor 16 in series with MOS circuit 14.
Referring now to FIG. 2, a first prior art method for operating powergated circuits 10, 20, and 30 is shown. The waveforms on nodes A and B are shown for each of circuits 10, 20 and 30. Circuit 10 uses waveform A, circuit 20 uses waveform B, and circuit 30 uses both waveforms A and B. Each of nodes A and B transition from an active mode to the standby mode, and back to the active mode. Node A is low (ground) and node B is high (VDD power supply voltage) during the active mode. To transition into the standby mode, node A is taken high (VDD power supply voltage) and node B is taken low (ground). The initial conditions are reasserted to transition back to the active mode. While the first prior art control levels shown in FIG. 2 significantly reduce the standby or leakage current of MOS circuit 14, the leakage current can be reduced still further.
Referring now to FIG. 3, a second prior art method for operating powergated circuits 10, 20, and 30 is shown. Node A is low (ground) and node B is high (VDD power supply voltage) during the active mode. To transition into the standby mode, node A is taken high (VDD power supply voltage+delta voltage) and node B is taken low (ground−delta voltage). The initial conditions are reasserted to transition back to the active mode. The second prior art control levels shown in FIG. 3 further reduce the standby or leakage current of MOS circuit 14 by establishing a negative VGS on transistors 12 and 16, but only in the standby mode.
What is desired is a further refinement in the manner of operating powergating circuits such that leakage current can be still further reduced.